1. Field of the Invention
The present invention relates to gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios.
2. Background Art
Commercialization of the Internet has proven to be a mainspring for incentives to improve network technologies. Development programs have pursued various approaches including strategies to leverage use of the existing Public Switched Telephone Network and plans to expand use of wireless technologies for networking applications. Both of these approaches (and others) entail the conversion of data between analog and digital formats. Therefore, it is expected that analog-to-digital converters (ADCS) and digital-to-analog converters (DACs) will continue to perform critical functions in many network applications.
FIG. 1 shows a process for converting an analog signal xe2x80x9cx[n]xe2x80x9d 102 to a digital signal xe2x80x9cz[n]xe2x80x9d 104 using an exemplary ADC 106. ADC 106 receives analog signal x[n] 102 and produces digital signal z[n] 104. Analog signal x[n] 102 comprises variations of a parameter (e.g., voltage) continuously with time. The variations in the parameter of analog signal x[n] 102 are maintained within a range between a lower value xe2x80x9cLOWxe2x80x9d 108 and a higher value xe2x80x9cHIGHxe2x80x9d 110. This is referred to as the xe2x80x9cswingxe2x80x9d of analog signal x[n] 102. Typically, analog signal x[n] 102 is characterized by a carrier frequency. Digital signal z[n] 104 comprises a sequence of discrete quantized values that, over time, tracks the parameter variations of analog signal x[n] 102. Typically, the quantized values of digital signal z[n] 104 are represented by binary numbers. A maximum value xe2x80x9cMAXxe2x80x9d 112 is defined by the number of different quantized values that can be produced by ADC 106.
FIG. 2 is a block diagram of ADC 106. ADC 106 comprises a sampling functional component 202 and a quantization functional component 204. Sampling functional component 202 records, at a sampling frequency, discrete values of analog signal x[n] 102. Typically, the sampling frequency is greater than or equal to the Nyquist frequency, which is twice the carrier frequency of analog signal x[n] 102. Quantization functional component 204 assigns a quantized value to represent each discrete sampled value, thereby producing digital signal z[n] 104.
The difference between digital signal z[n] 104 and analog signal x[n] 102 is referred to as quantization error e[n]. Ideally, there is a direct relationship between the values of analog signal x[n] 102 and digital signal z[n] 104 at corresponding points in time. In reality, the use of a limited number of quantized values for digital signal z[n] 104 dictates that, in some instances, values of analog signal x[n] 102 must be approximated. It is desirable to minimize quantization error e[n], which is an unwanted byproduct of the quantization process.
FIG. 3 illustrates the process within quantization functional component 204. The range of parameter variations of analog signal x[n] 102 is divided into a number of equal-sized subranges. The number of equal-sized subranges is defined by the value of MAX 112. If, for example, MAX 112 equals four, then the range of parameter variations of analog signal x[n] 102 is divided into four subranges, each measuring one-quarter of the range between LOW 108 and HIGH 110. A subrange xe2x80x9cAxe2x80x9d 302 extends from LOW 108 to a value at a point xe2x80x9cQ1xe2x80x9d 304. A subrange xe2x80x9cBxe2x80x9d 306 extends from Q1304 to a value at a point xe2x80x9cQ2xe2x80x9d 308. A subrange xe2x80x9cCxe2x80x9d 310 extends from Q2308 to a value at a point xe2x80x9cQ3xe2x80x9d 312. A subrange xe2x80x9cDxe2x80x9d 314 extends from Q3312 to HIGH 110.
Both analog signal x[n] 102 and digital signal z[n] 104 are usually biased by specific values that can obscure the underlying relationship between the two signals. This relationship is more readily explained when analog signal x[n] 102 is understood to be centered at a point measuring one-half of the range between LOW 108 and HIGH 110. In the present example, this point is Q2308. By translating the actual value of Q2308 to zero and the remaining points in analog signal x[n] 102 accordingly, the bias value is removed from analog signal x[n] 102. Therefore, quantized values derived from this translated analog signal x[n] 102 correspond to digital signal z[n] 104 with its bias value removed.
To minimize quantization error e[n], a quantized value is located in each subrange at a point measuring one-half of the subrange. Each quantized value can be represented by a binary number. For example, a first quantized value xe2x80x9caxe2x80x9d316, represented by binary number zero, is located at the midpoint of subrange A 302. A second quantized value xe2x80x9cbxe2x80x9d318, represented by binary number one, is located at the midpoint of subrange B 306. A third quantized value xe2x80x9ccxe2x80x9d320, represented by binary number two, is located at the midpoint of subrange C 310. A fourth quantized value xe2x80x9cdxe2x80x9d322, represented by binary number three, is located at the midpoint of subrange D 314.
The number of subranges determines the degree of resolution of ADC 106. Degree of resolution is typically expressed as the number of binary digits (i.e., bits) in the quantized values that can be produced by ADC 106. ADC 106 is characterized by its sampling frequency and its degree of resolution. The ability of ADC 106 to digitize analog signal x[n] 102 faithfully is a direct function of both of these. As the sampling frequency is increased, analog signal x[n] 102 is sampled at more points in time. As the degree of resolution is refined, the differences between digital signal z[n] 104 and analog signal x[n] 102 are minimized.
FIG. 4 is a graph 400 of bias-free values of digital signal z[n] 104 as a function of bias-free values of analog signal x[n] 102. A dashed line 402 represents the ideal direct relationship between the values of analog signal x[n] 102 and digital signal z[n] 104. The slope of dashed line 402 corresponds to the gain of ADC 106. A shaded portion 404 between graph 400 and dashed line 402 corresponds to quantization error e[n]. The same error pattern applies to each subrange. The measure of each subrange is referred to as the measure of a Least Significant Bit (LSB).
Statistical methods are often used to analyze quantization error e[n]. FIG. 5 is a graph 500 of a probability density xe2x80x9cP(p)xe2x80x9d 502 of a subrange of digital signal z[n] 104 as a function of the parameter xe2x80x9cpxe2x80x9d 504 of analog signal x[n] 102. Probability density P(p) 502 is centered at the midpoint of the subrange (i.e., at a 316, b 318, c 320, or d 322). Probability density P(p) 502 corresponds to quantization error e[n]. Probability density P(p) 502 shows that digital signal z[n] 104 has the same value throughout the subrange, where the subrange extends on either side of its midpoint for a measure equal to one-half of the LSB. The constant value of digital signal z[n] 104 within each subrange and its relation ship to quantization error e[n] is also shown by graph 400.
Further analysis of quantization error e[n] is often performed in the frequency domain. FIG. 6 is a graph 600 of probability density P(p) 502 in the frequency domain. Graph 600 shows an xe2x80x9cabsolute value of pxe2x80x9d 602 as a function of frequency xe2x80x9cfreqxe2x80x9d 604. In the frequency domain, quantization error e[n] is recast as quantization noise n[n]. Quantization noise n[n] has a constant value for all frequencies. This is referred to as xe2x80x9cwhite noise.xe2x80x9d The white noise of ADC 106 is directly proportional to the measure of the LSB and indirectly proportional to the square root of the sampling frequency. Thus, quantization noise n[n] (and, by transformation, quantization error e[n]) can be minimized by increasing sampling frequency or decreasing the measure of the LSB. The measure of the LSB can be reduced by increasing the number of subranges into which the range of analog signal x[n] 102 is divided (i.e., increasing the number of bits that can be produced by ADC 106).
Because ADCs find uses in a wide variety of applications, design of these circuits has evolved along many paths to yield several distinct architectures, including xe2x80x9cflash,xe2x80x9d xe2x80x9cpipelined,xe2x80x9d xe2x80x9csuccessive approximation,xe2x80x9d and xe2x80x9cdelta sigma.xe2x80x9d These designs are well known to those skilled in the art and their functional components vary in some respects from those of exemplary ADC 106. Each architecture has its benefits and drawbacks. Paramount among these is a tradeoff between bandwidth and degree of resolution. FIG. 7 is a graph 700 that shows the tradeoff between bandwidth and degree of resolution for the various ADC architectures. Graph 700 comprises a xe2x80x9cdegree of resolutionxe2x80x9d axis 702 and a xe2x80x9cbandwidthxe2x80x9d axis 704. The relative positions of the different ADC architectures are plotted with respect to axes 702, 704: a xe2x80x9cflashxe2x80x9d region 706, a xe2x80x9cpipelinedxe2x80x9d region 708, a xe2x80x9csuccessive approximationxe2x80x9d region 710, and a xe2x80x9cdelta sigmaxe2x80x9d region 712.
In the design of network technologies, data conversion has often presented itself as a bottleneck that impedes the rate at which information is transmitted. Traditionally, those ADC architectures that can support large bandwidths for rapid transfers of data have been favored for network applications. Because much of the circuitry of a delta sigma ADC architecture is analog, its bandwidth is limited by the processing speed of its analog circuits.
However, emerging applications, such as full-motion video and voice over Internet, require high resolution data conversion. Fortunately, improvements in the methods of fabricating integrated electronic circuits have increased not only the processing speed and number of devices, but also the variety of devices (such as linear capacitors) that can be fabricated on a given area of substrate material. Delta sigma ADCs have benefited from these developments, which have facilitated the use of delta sigma ADCs in network applications.
FIG. 8 is a block diagram of a first-order, single-stage, single-bit delta sigma ADC 800. ADC 800 comprises a first-order, single-stage, single-bit delta sigma modulator 802 and a digital decimator 804 connected at a node xe2x80x9cNoxe2x80x9d 806 along a signal path 808. Modulator 802 comprises a summing node xe2x80x9cxcexa30xe2x80x9d 810, an integrator 812, a single-bit quantizer 814, and a DAC 816. Summing node xcexa30 810, integrator 812, and quantizer 814 are connected, respectively, in series along signal path 808. Integrator 812 has a gain xe2x80x9ca1xe2x80x9d. Gain a1 is determined empirically and is set to a value such that modulator 802 functions with stability to process analog signal x[n] 102. Typically, gain a1 has a value between zero and one. DAC 816 is connected in parallel with signal path 808 between node N0 806 and summing node xcexa30 810. Decimator 804 comprises a lowpass digital filter 818 and a downsampler 820 connected, respectively, in series along signal path 808. Analog signal x[n] 102 is received by ADC 800, at an input 822, and converted into digital signal z[n] 104, produced at an output 824.
Initially, analog signal x[n] 102 passes through summing node xcexa30 810 and is sampled by integrator 812. Integrator 812 integrates analog signal x[n] 102 over a given period of time to produce an integrated signal xe2x80x9cv[n]xe2x80x9d 826. Integrated signal v[n] 826 is transmitted to single-bit quantizer 814. Single-bit quantizer 814 rounds integrated signal v[n] 826 to the closest of two preset levels (i.e., a single bit) to produce a quantized signal xe2x80x9cy[n]xe2x80x9d 828. To minimize the difference between quantized signal y[n] 828 and analog signal x[n] 102, quantized signal y[n] 824 is transmitted to DAC 816 and converted to produce an analog feedback signal xe2x80x9cfbk[n]xe2x80x9d 830, which is fed back to summing node xcexa30 810. Quantizer 814 and DAC 816 have a combined gain xe2x80x9ck1xe2x80x9d defined as shown in Eq. (1):
k1xe2x89xa1fbk[n]/[n],xe2x80x83xe2x80x83Eq. (1) 
where both analog feedback signal fbk[n] 830 and integrated signal v[n] 826 are analog signals.
At summing node xcexa30 810, analog feedback signal fbk[n] 830 is subtracted from analog signal x[n] 102 to produce an analog difference signal xe2x80x9cu[n]xe2x80x9d 832. Analog difference signal u[n] 832 passes into integrator 812 to repeat the process described above. Essentially, integrator 812 integrates the difference between quantized signal y[n] 828 and analog signal x[n] 102. Over a large number of samples, integrator 812 forces this difference to approach zero. Thus, analog signal x[n] 102 is received by modulator 802, at input 822, and converted into quantized signal y[n] 828, produced at node No 806. Input 822 is an input and node N. 806 is an output of modulator 802.
FIG. 9 is a graph 900 of bias-free values of quantized signal y[n] 828, produced by single-bit quantizer 814, as a function of bias-free values of analog signal x[n] 102. With analog signal x[n] 102 centered at a point measuring one-half of the range between LOW 108 and HIGH 110 (e.g., point Q2308 from the example above), quantizer 814 divides analog signal x[n] 102 into two subranges. Quantizer 814 assigns a lower value xe2x80x9cLOWERxe2x80x9d 902 to those values of analog signal x[n] 102 that are less than the midpoint (e.g., Q2308) value, and a higher value xe2x80x9cHIGHERxe2x80x9d 904 to those values of analog signal x[n] 102 that are greater than the midpoint (e.g., Q2308) value. Typically, LOWER 902 is the lowest quantized value and HIGHER 904 is the highest quantized value that can be produced by quantizer 814.
Returning to FIG. 8, quantized signal y[n] 828 from modulator 802 comprises a stream of quantized values. Each quantized value is either LOWER 902 or HIGHER 904 (i.e., a single bit of resolution). Typically, this stream is produced at a modulator frequency that is several times greater than the carrier frequency of analog signal x[n] 102. The ratio of the modulator frequency to the Nyquist frequency is referred to as the oversampling ratio (OSR).
Decimator 804 acts to lowpass filter and downsample quantized signal y[n] 828. Quantized signal y[n] 828 is transmitted to lowpass digital filter 818, which performs a sophisticated form of averaging on the data stream to produce a high resolution signal xe2x80x9cw[n]xe2x80x9d 834. A maximum value xe2x80x9cMAXIMUMxe2x80x9d is defined by the number of different quantized values that can be produced by filter 818. High resolution signal w[n] 834 also comprises a stream of quantized values. However, each quantized value can be any of the different quantized values (i.e., multiple bits of resolution) that can be produced by filter 818. High resolution signal w[n] 834 also comprises a stream of quantized values. However, each quantized value can be any of the different quantized values (i.e., multiple bits of resolution) that can be produced by filter 818.
High resolution signal w[n] 834 emerges from filter 818 at a frequency too high for subsequent digital signal processing. High resolution signal w[n] 834 is transmitted to downsampler 820, which resamples high resolution signal w[n] 834 to produce digital signal z[n] 104. Digital signal z[n] 104 enjoys the same high resolution as high resolution signal w[n] 834, but at a digital processing frequency. Typically, the digital processing frequency is greater than or equal to the Nyquist frequency. Thus, quantized signal y[n] 828 is received by decimator 804, at node N0 806, and converted into digital signal z[n] 104, produced at output 824. Node N0 806 is an input and output 824 is an output of decimator 804.
The usefulness of the high resolution of ADC 800 turns on its ability to minimize quantization noise n, which is an unwanted byproduct of the quantization process. Fortunately, it is a feature of modulator 802 that it acts as a highpass filter for quantization noise n, much of which can be removed by lowpass digital filter 818. This capability is more readily explained by analyzing modulator 802 in the frequency domain.
FIG. 10 is a block diagram of first-order, single-stage, single-bit delta sigma modulator 802 recast as a frequency domain model 1000 for a continuous time implementation. In model 1000, integrator 812 is replaced by an analog filter 1002 with gain a1, single-bit quantizer 814 is replaced by a gain element 1004 connected in series with a second summing node xe2x80x9cxcexa31xe2x80x9d 1006. (First summing node So 810 remains a component of model 1000.) A quantization noise xe2x80x9cnxe2x80x9d 1008 is added at second summing node xcexa311006. DAC 816 is replaced by a parallel connection xe2x80x9cL0xe2x80x9d 1010 between node N0 806 and summing node xcexa30 810. Combined gain k1 of quantizer 814 and DAC 816 is realized by assigning gain k1 to gain element 1004 and a gain of one to L0 1010.
In model 1000, analog signal x 102 initially passes through summing node xcexa30 810 and into analog filter 1002. Analog filter 1002 has a transfer function with an amplitude that is inversely proportional to a frequency xe2x80x9cfxe2x80x9d of analog signal x 102 as shown in Eq. (2):
v=a1u/f.xe2x80x83xe2x80x83Eq. (2) 
Single-bit quantizer 814 is modeled as gain element 1004 connected in series with second summing node xcexa31 1006 to reflect the concept of treating quantization noise n 1008 as an unwanted byproduct of the quantization process. A transfer function of single-bit quantizer 814 can be expressed as shown in Eq. (3):
y=vk1+n.xe2x80x83xe2x80x83Eq. (3) 
In reality, both gain k1 and quantization noise n 1008 are unknown. Because single-bit quantizer 814 does not produce any quantized values that are in between LOWER 902 and HIGHER 904 (its lowest and highest quantized values), gain k1 is essentially indeterminate. However, for analysis purposes, it is desirable to model quantization noise n 1008 as white noise and to set an overall gain of modulator 802, the product of gain a1 and gain k1, equal to one. Both of these attributes can be realized for analysis purposes by assuming that k1=1/a1.
In modulator 802, the addition of quantization noise n 1008 after integrator 812, but before production of analog feedback signal fbk 830 enables modulator 802 to shape quantization noise n 1008 as a function of frequency f. Quantized signal y 828 as a function of frequency f can be expressed as shown in Eq. (4):
y=[x+nf]/[f+1].xe2x80x83xe2x80x83Eq. (4) 
Eq. (4) shows that modulator 802 acts as a highpass filter for quantization noise n 1008. The coupling of modulator 802 with lowpass digital filter 818 of decimator 804 enables ADC 800 to enjoy a relatively high signal-to-noise ratio (SNR) in comparison with other ADC architectures. As a xe2x80x9crule of thumbxe2x80x9d, the SNR for ADC 800 improves by 9 dB for every doubling of its OSR.
SNR is an important figure of merit for ADC performance. Improvements in the methods of fabricating integrated electronic circuits have reduced the size of electron devices. This has enabled ADC 800 to be designed to consume less power. However, reduced power consumption is often realized in part by using lower power supply voltages. Integrator 812 is implemented using an operational amplifier. Because some of the range between supply voltages to an operational amplifier must be consumed to support holding active load devices and current sources in saturation, only the remaining portion of this range is available for the output swing of the operational amplifier. This remaining portion is referred to as the dynamic range of the operational amplifier. So that ADC 800 does not suffer from nonidealities caused by the operational amplifier that implements integrator 812, it is important that the swing of integrated signal x[n] 826 remain within the dynamic range of the operational amplifier.
Two other important figures of merit for ADC performance are dynamic range (DR) and overload level (OL). DR, which is different from the dynamic range of the operational amplifier used to implement integrator 812, is the maximum SNR achievable for a given ADC topology. Typically, the swing of analog signal x[n] 102 is maintained within a range. Measures of the SNR vary as a function of the measure of this range. OL is the maximum range at which the SNR degrades to 6 dB less than its DR value. FIG. 11 is a graph 1100 of the xe2x80x9cSNRxe2x80x9d 1102 as a function of a range xe2x80x9crxe2x80x9d 1104 of the swing of analog signal x[n] 102. Both SNR 1102 and r 1104 are expressed in decibels. Graph 1100 shows a value xe2x80x9cDRxe2x80x9d 1106 at the point of maximum SNR 1102 and a value xe2x80x9cOLxe2x80x9d 1108 at the maximum point of range r 1104 at which SNR degrades to 6 dB less than value DR 1106.
First order, single-stage, single-bit delta sigma modulator 802 is a basic design for a sigma delta modulator. Variations to this basic design have been introduced to improve these figures of merit.
FIG. 12 is a block diagram of a first-order, single-stage, two-bit delta sigma modulator 1200. Modulator 1200 comprises summing node xcexa30 810, integrator 812, a two-bit quantizer 1202, and a two-bit DAC 1204. Summing node xcexa30 810, integrator 812, and two-bit quantizer 1202 are connected, respectively, in series along signal path 808. Integrator 812 has a gain xe2x80x9ca2xe2x80x9d. Gain a2 is determined empirically and is set to a value such that modulator 1200 functions with stability to process analog signal x[n] 102. Typically, gain a2 has a value between zero and one. Two-bit DAC 1204 is connected in parallel with signal path 808 between node N0 806 and summing node xcexa30 810. Two-bit quantizer 1202 and a two-bit DAC 1204 have a combined gain xe2x80x9ck2xe2x80x9d. Analog signal x[n] 102 is received by modulator 1200, at input 822, and converted into a two-bit quantized signal xe2x80x9cy, [n]xe2x80x9d 1206, produced at node N0 806. Input 822 is an input and node No 806 is an output of modulator 1200.
FIG. 13 is a graph 1300 of bias-free values of two-bit quantized signal y1[n] 1206, produced by two-bit quantizer 1202, as a function of bias-free values of analog signal x[n] 102. Two-bit quantizer 1202 divides analog signal x[n] 102 into four subranges. However, by using LOWER 902 and HIGHER 904, two-bit quantizer 1202 only needs to divide two-bit quantized signal y, [n] 1206 into three subranges. Therefore, two-bit quantizer 1202 defines a third value xe2x80x9cHIGHER/3xe2x80x9d 1302 at a point one-third of the range from HIGHER 904 to LOWER 902, and a fourth value xe2x80x9cLOWER/3xe2x80x9d 1304 at a point one-third of the range from LOWER 902 to HIGHER 904.
Because it is desirable that two-bit quantizer 1202 exhibit a similar error pattern to that shown at graph 400 for ADC 106, dashed line 1306 represents the ideal direct relationship between the values of analog signal x[n] 102 and two-bit quantized signal y1[n] 1206. Therefore, with analog signal x[n] 102 centered at a point measuring one-half of the range between LOW 108 and HIGH 110 (e.g., point Q2308 from the example above), two-bit quantizer 1202 defines a subrange xe2x80x9cExe2x80x9d 1308 that extends from LOW 108 to a point xe2x80x9cLOW2/3xe2x80x9d 1310 located two-thirds of the range from Q2308 to LOW 108. A subrange xe2x80x9cFxe2x80x9d 1312 extends from LOW2/31310 to Q2308. A subrange xe2x80x9cGxe2x80x9d 1314 extends from Q2308 to a point xe2x80x9cMGH2/3xe2x80x9d 1316 located two-thirds of the range from Q2308 to HIGH 110. A subrange xe2x80x9cHxe2x80x9d 1318 extends from HIGH2/31316 to HIGH 110.
Two-bit quantizer 1202 assigns LOWER 902 to those values of analog signal x[n] 102 that are between LOW 108 and LOW2/31310, LOWER/31304 to those values of analog signal x[n] 102 that are between LOW2/31310 and Q2308, HIGHER/31302 to those values of analog signal x[n] 102 that are between Q2308 and HIGH2/31316, and HIGHER 904 to those values of analog signal x[n] 102 that are between HIGH2/31316 and HIGH 110.
Because two-bit quantizer 1202 divides analog signal x[n] 102 into four subranges, the measure of the LSB for two-bit quantizer 1202 is less than the measure of the LSB for quantizer 814. As graph 600 shows white noise to be directly proportional to the measure of the LSB, it follows that quantization noise n 1008 produced by modulator 1200 is less than quantization noise n 1008 produced by modulator 802. A similar analysis can be used to assess other multi-bit delta sigma modulators. As a rule of thumb, the SNR for a delta sigma ADC that incorporates a multi-bit delta sigma modulator improves by 6 dB for each additional bit of resolution beyond the second bit. However, the use of two-bit quantizer 1202 imposes tough demands on the linearity of two-bit DAC 1204, which must be nearly as linear as modulator 1202 as a whole. Multi-bit DACs with such precise linearity cannot be easily fabricated using Very Large Scale Integration technology.
FIG. 14 is a block diagram of a second-order, single-stage, single-bit delta sigma modulator 1400. Modulator 1400 comprises first summing node 10810, first integrator 812, a second summing node xe2x80x9cxcexa32xe2x80x9d 1402, a second integrator 1404, single-bit quantizer 814, and DAC 816. First summing node 10810, first integrator 812, second summing node xcexa32 1402, second integrator 1404, and quantizer 814 are connected, respectively, in series along signal path 808. First integrator 812 has a gain of xe2x80x9ca3xe2x80x9d. Second integrator 1404 has a gain of xe2x80x9ca4xe2x80x9d. Gains a3 and a4 are determined empirically and are set to values such that modulator 1400 functions with stability to process analog signal x[n] 102. Typically, gains a3 and a4 have values between zero and one. DAC 816 is connected in parallel with signal path 808 between node No 806 and summing nodes xcexa30 810 and xcexa32 1402. Quantizer 814 and DAC 816 have a combined gain k1. For analysis purposes, k1=1/a3a4. A higher order compensation gain element xe2x80x9c2a3xe2x80x9d 1406 is connected between DAC 816 and second summing node xcexa32 1402.
Higher order compensation gain element 2a3 1406 has a gain of xe2x80x9c2a3xe2x80x9d. Analog signal x[n] 102 is received by modulator 1400, at input 822, and converted into quantized signal y[n] 828, produced at node No 806. Input 822 is an input and node N0 806 is an output of modulator 1400.
In a continuous time implementation, second integrator 1404 acts as a second highpass filter for quantization noise n 1008. Higher order compensation gain element 2a3 1406 enables quantized signal y 828 to be expressed strictly as a second order function of frequency f as shown in Eq. (5):
y=[x+nf2]/[f+1]2.xe2x80x83xe2x80x83Eq. (5) 
Thus, a delta sigma ADC that incorporates modulator 1400 can enjoy a better SNR than ADC 800. As a rule of thumb, the SNR for a delta sigma ADC that incorporates modulator 1400 improves by 15 dB for every doubling of its OSR.
A similar analysis can be used to assess higher order delta sigma modulators.
However, empirical studies have shown that, while delta sigma ADCs that incorporate higher order modulators are relatively insensitive to nonidealities in their functional components, the stability of these circuits rapidly deteriorates beyond the second order.
FIG. 15 is a block diagram of a second-order, two-stage, single-bit delta sigma modulator 1500. Modulator 1500 comprises a first modulator stage 1502, a coupling stage 1504, a second modulator stage 1506, and a noise cancellation logic stage 1508.
First modulator stage 1502 comprises first summing node S 810, first integrator 812, first single-bit quantizer 814, and first DAC 816. First summing node So 810, first integrator 812, and first quantizer 814 are connected, respectively, in series along signal path 808. First integrator 812 has gain a1. Gain a1 is determined empirically and is set to a value such that first modulator stage 1502 functions with stability to process analog signal x[n] 102. Typically, gain a1 has a value between zero and one. First DAC 816 is connected in parallel with signal path 808 between node N0 806 and first summing node xcexa30 810. First quantizer 814 and first DAC 816 have a combined gain k1. For analysis purposes, k1=1/a1. Analog signal x[n] 102 is received by first modulator stage 1502, at input 822, and converted into a first modulated signal xe2x80x9cy2[n]xe2x80x9d 1510, produced at node N0 806. Input 822 is an input and node N0 806 is an output of modulator stage 1502.
Coupling stage 1504 comprises a normalization gain element xe2x80x9c1/a1xe2x80x9d 1512, a noise reduction gain element xe2x80x9cb1xe2x80x9d 1514, a stability correction gain element xe2x80x9cc1xe2x80x9d 1516, and a second summing node xe2x80x9cxcexa33xe2x80x9d 1518. Normalization gain element 1/a1 1512 amplifies integrated signal v[n] 826 by a gain of xe2x80x9c1/a1xe2x80x9d, the inverse of gain a1 of first integrator 812, to produce an amplified integrated signal xe2x80x9c1/a1v[n]xe2x80x9d 1520. This normalizes integrated signal v[n] 826. Noise reduction gain element b1 1514 amplifies analog feedback signal fbk[n] 830 by a gain of xe2x80x9cb1xe2x80x9d, to produce an amplified analog feedback signal xe2x80x9cblfbk[n]xe2x80x9d 1522. (When a modulator stage has more than one integrator, each with a gain xe2x80x9ca1xe2x80x9d, often there is a relationship between gain b1 and a ratio of the gain a1 of the integrator immediately preceding the quantizer to the product of all gains a1.) Second summing node xcexa33 1518 subtracts amplified analog feedback signal b1fbk[n] 1522 from amplified integrated signal 1/a1v[n] 1520 to yield a difference signal xe2x80x9cd[n]xe2x80x9d 1524. This reduces the amplitude distribution of quantization noise n[n] that is embedded within difference signal d[n] 1524. Stability correction gain element c1 1516 amplifies difference signal d[n] 1524 by a gain of xe2x80x9cc1xe2x80x9d to produce a second analog signal xe2x80x9cx2[n]xe2x80x9d 1526. Thus, integrated signal v[n] 826 and analog feedback signal fbk[n] 830 are received by coupling stage 1504 and converted into second analog signal x2[n] 1526, produced at a node xe2x80x9cN1xe2x80x9d 1528.
In general, when coupling stage 1504 is preceded by a modulator stage with a single-bit quantizer, gain c1 typically has a value between zero and one. Preferably, gain c1 is set equal to a power of two. This simplifies the configuration of noise cancellation logic stage 1508. Always, gain c1 is set so that the swing of an integrated signal (e.g., v[n] 826) produced by a second integrator 1530 of second modulator stage 1506 remains within the dynamic range of the operational amplifier used to implement second integrator 1530. Often there is an inverse relationship between gain c1 and the product of gains a1 of the integrators of the subsequent modulator stage.
Second modulator stage 1506 comprises a third summing node xe2x80x9cxcexa34xe2x80x9d 1532, second integrator 1530, a second single-bit quantizer 1534, and a second DAC 1536. Third summing node xcexa34 1532, second integrator 1530, and second quantizer 1534 are connected, respectively, in series along signal path 808. Second integrator 1530 has a gain of xe2x80x9ca5xe2x80x9d. Gain a5 is determined empirically and is set to a value such that second modulator stage 1506 functions with stability to process second analog signal x2[n] 1526. Typically, gain a5 has a value between zero and one. Second DAC 1536 is connected in parallel with signal path 808 between a node xe2x80x9cN2xe2x80x9d 1538 and third summing node xcexa34 1532. Second quantizer 1534 and second DAC 1536 have a combined gain of xe2x80x9ck3xe2x80x9d. For analysis purposes, k3=1/a5. Second analog signal x2[n] 1526 is received by second modulator stage 1506, at node N1 1528, and converted into a second modulated signal xe2x80x9cy3[n]xe2x80x9d 1540, produced at node N2 1538. Node N1 1528 is an input and node N2 1538 is an output of second modulator stage 1506.
Noise cancellation logic stage 1508 comprises a first delay element xe2x80x9cD1xe2x80x9d 1542, a second delay element xe2x80x9cD2xe2x80x9d 1544, a noise cancellation logic gain element xe2x80x9c(b1xe2x88x921)xe2x80x9d 1546, a stability normalization gain element xe2x80x9c1/c1xe2x80x9d 1548, a fourth summing node xe2x80x9cxcexa35xe2x80x9d 1550, a fifth summing node xe2x80x9cxcexa36xe2x80x9d 1552, and a sixth summing node xe2x80x9cxcexa37xe2x80x9d 1554. First delay element D1 1542 receives first modulated signal y2[n] 1510 and delays it by a processing period to produce a delayed modulated signal xe2x80x9cdel[n]xe2x80x9d 1556. Noise cancellation logic gain element (b1xe2x88x921) 1546 receives delayed modulated signal del[n] 1556 and amplifies it by a gain of xe2x80x9c(b1xe2x88x921)xe2x80x9d, one less than gain b1 of noise reduction gain element b1 1514, to produce an amplified delayed modulated signal xe2x80x9c(b1xe2x88x921)del[n]xe2x80x9d 1558. This facilitates noise cancellation. Stability normalization gain element 1/c1 1548 receives second modulated signal y3[n] 1540 and amplifies it by a gain xe2x80x9c1/c1xe2x80x9d, the inverse of gain c1 of stability correction gain element c1 1516, to produce an amplified modulated signal xe2x80x9cy3[n]/c1xe2x80x9d 1560. This normalizes second modulated signal y3[n] 1540. Fourth summing node xcexa35 1550 receives amplified delayed modulated signal (b1xe2x88x921)del[n] 1558 and adds it to amplified modulated signal y3[n]/c1 1560 to produce a sum modulated signal xe2x80x9csum[n]xe2x80x9d 1562. Second delay element D2 1544 receives sum modulated signal sum[n] 1562 and delays it by the processing period to produce a delayed sum modulated signal xe2x80x9cdelsum[n]xe2x80x9d 1564. Fifth summing node xcexa36 1552 receives delayed sum modulated signal delsum[n] 1564 and subtracts it from sum modulated signal sum[n] 1562 to produce a difference modulated signal xe2x80x9cdiff[n]xe2x80x9d 1566. Sixth summing node xcexa37 1554 receives delayed modulated signal del[n] 1556 and adds it to difference modulated signal diff[n] 1566 to produce quantized signal y[n] 828. Thus, first modulated signal y2[n] 1510 and second modulated signal y3[n] 1540 are received by noise cancellation logic stage 1508, respectively at nodes N0 806 and N2 1538, and converted into quantized signal y[n] 828, produced at a node xe2x80x9cN3xe2x80x9d 1568. Nodes N0 806 and N2 1538 are inputs and node N3 1568 is an output of noise cancellation logic stage 1508.
The topology of multistage delta sigma modulators can be referenced by the order of each modulator stage. For example, modulator 1500 can be referred to as a 1-1 delta sigma modulator. Likewise, a delta sigma modulator that has a second order first stage, a first order second stage, and a first order third stage can be referred to as a 2-1-1 delta sigma modulator. Other multistage delta sigma modulators are similarly referenced by the order of each modulator stage.
Because the circuitry of a delta sigma ADC architecture includes both analog and digital components, the transfer functions of these components are often expressed in the discrete time xe2x80x9czxe2x80x9d domain to account for the latency period between the time at which analog signal x[n] 102 is sampled and the time at which digital signal z[n] 104 is produced. Multistage delta sigma modulators, such as modulator 1500, particularly lend themselves to analysis in the discrete time domain.
FIG. 16 is a block diagram of second-order, two-stage, single-bit delta sigma modulator 1500 recast as a discrete time domain model 1600. In model 1600, first integrator 812 is replaced by a first discrete time integrator 1602, and first single-bit quantizer 814 is replaced by a first gain element 1604 connected in series with a second summing node xe2x80x9cxcexa38xe2x80x9d 1606. (First summing node xcexa30 810 remains a component of model 1600.) First discrete time integrator 1602 has gain a1. First gain element 1604 has gain k1. First DAC 816 is replaced by a first parallel connection xe2x80x9cL1xe2x80x9d 1608 between node N0 806 and first summing node xcexa30 810. Likewise, second integrator 1530 is replaced by a second discrete time integrator 1610, and second single-bit quantizer 1534 is replaced by a second gain element 1612 connected in series with a fourth summing node xe2x80x9cxcexa39xe2x80x9d 1614. (Third summing node xcexa34 1532 remains a component of model 1600.) Second discrete time integrator 1610 has gain a5. Second gain element 1612 has gain k3. Second DAC 1536 is replaced by a second parallel connection xe2x80x9cL2xe2x80x9d 1616 between node N2 1538 and third summing node xcexa34 1532. Each of first and second discrete time integrators 1602, 1610 has a transfer function of xe2x80x9czxe2x88x921/(1xe2x88x92zxe2x88x921)xe2x80x9d. Coupling stage 1504 remains a component of model 1600. Noise cancellation logic gain element (b1xe2x88x921) 1546, stability normalization gain element 1/c1 1548, summing node xcexa35 1550, and summing node xcexa37 1554 remain components of model 1600. First delay element D1 1542 is replace by a digital delay element 1618. Digital delay element 1618 has a transfer function of xe2x80x9czxe2x88x921xe2x80x9d. Second delay element D2 1544 and summing node xcexa36 1552 are replaced by a digital differentiator 1620. Digital differentiator 1620 has a transfer function of xe2x80x9c(1xe2x88x92zxe2x88x921)xe2x80x9d.
In model 1600, a first quantization noise xe2x80x9cn,[n]xe2x80x9d 1622 is added at second summing node xcexa38 1606, and a second quantization noise xe2x80x9cn2[n]xe2x80x9d 1624 is added at fourth summing node xcexa39 1614.
Recalling that gain a1 is set equal to the inverse of gain k1, first modulated signal y2[n] 1510 can be expressed as a function of analog signal x[n] 102, transfer function, zxe2x88x921/(1xe2x88x92zxe2x88x921), of first discrete time integrator 1602, gain a1 of first discrete time integrator 1602, gain k1 of first gain element 1604, and first quantization noise n1[n] 1622 as shown in Eq. (6):
y2[n]=x[n]zxe2x88x921+n1[n](1xe2x88x92zxe2x88x921).xe2x80x83xe2x80x83Eq. (6) 
Second analog signal x2[n] 1526 can be expressed as a function of first modulated signal y2[n] 1510, first quantization noise n1[n] 1622, normalization gain element 1/a1 1512, noise cancellation setup gain element b1 1514, and stability correction gain element c1 1516 as shown in Eq. (7):
x2[n]=c1(1xe2x88x92b1)y2[n]xe2x88x92c1n1[n]xe2x80x83xe2x80x83Eq. (7) 
Recalling that a5 is set equal to the inverse of k3, second modulated signal y3[n] 1540 can be expressed as a function of second analog signal x2[n] 1526, transfer function, zxe2x88x921/(1xe2x88x92zxe2x88x921), of second discrete time integrator 1610, gain a5 of second discrete time integrator 1610, gain k3 of second gain element 1612, and second quantization noise n2[n] 1624 as shown in Eq. (8):
y3[n]=x2[n]zxe2x88x921+n2[n](1xe2x88x92zxe2x88x921).xe2x80x83xe2x80x83Eq. (8) 
Using Eq. (7), Eq. (8) can be simplified as shown in Eq. (9):
y3[n]=c1(1xe2x88x92b1)y2[n]zxe2x88x921xe2x88x92c1n1[n]zxe2x88x921+n2[n](1xe2x88x92zxe2x88x921).xe2x80x83xe2x80x83Eq. (9) 
Quantized signal y[n] 828 can be expressed as a function of first modulated signal y2[n] 1510, second modulated signal y3[n] 1540, transfer function, z1, of digital delay element 1618, transfer function, 1xe2x88x92zxe2x88x921, of digital differentiator 1620, noise cancellation logic gain element (b1xe2x88x921) 1546, and stability normalization gain element 1/c1 1548 as shown in Eq. (10):
y[n]=y2[n]zxe2x88x921+[(b1xe2x88x921)y2[n]zxe2x88x921+y3[n]/c1][1xe2x88x92zxe2x88x921].xe2x80x83xe2x80x83Eq. (10) 
Using Eq. (9), Eq. (10) can be simplified as shown in Eq. (11):
y[n]=y2[n]zxe2x88x921xe2x88x92n1[n]zxe2x88x921(1xe2x88x92zxe2x88x921)+n2[n]/c1(1xe2x88x92zxe2x88x921)2.xe2x80x83xe2x80x83Eq. (11) 
Using Eq. (6), Eq. (11) can be simplified as shown in Eq. (12):
y[n]=x[n]zxe2x88x922+n2[n]/c1(1xe2x88x92zxe2x88x921)2.xe2x80x83xe2x80x83Eq. (12) 
Eq. (12) shows that modulator 1500 acts to shape the quantization noise n[n] that is embedded within quantized signal y[n] 828. First quantization noise n1[n] 1622 from first modulator stage 1502 is canceled and second quantization noise n2[n] 1624 from second modulator stage 1506 is desirably reduced to a second order effect. However, because gain c1 of stability correction gain element c1 1516 typically has a value between zero and one, modulator 1500 also undesirably amplifies second quantization noise n2[n] 1624.
A similar analysis can be used to assess other multistage delta sigma modulators. Delta sigma ADCs that incorporate multiple stages of low order modulators can provide a stable means for realizing the noise-shaping capabilities of high order, single-stage modulators. However, empirical studies have shown that multistage topologies have a more pronounced degree of sensitivity for nonidealities within their functional components.
More complex delta sigma modulator topologies can be designed by combining and/or expanding upon the principles explained above with regards to modulators 802, 1200, 1400, and 1500. For a given application, a more complex topology would enable a designer to optimize desirable features while minimizing undesirable ones.
A systematic study of delta sigma modulator topologies is presented in Marques, A. et al., IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45:1232-1241 (September 1998), which is incorporated herein by reference. Marques et al. examines the relationships among the gain scaling coefficients of integrators (i.e., a1, a2, etc.) and coupling stages gain elements (i.e., b1, c1, etc.) of various multistage delta sigma modulator topologies to determine what values should be assigned to each of these gain scaling coefficients to maximize the DRs. Marques et al. teaches specific values for each of these gain scaling coefficients. An unfortunate consequence of the specific values taught by Marques et al. is that they cause the quantization errors e[n] embedded within quantized signals y[n] 828 to be amplified. This limits the SNRs of the topologies. What are needed are gain scaling coefficients that can increase the SNRs of the various multistage delta sigma modulator topologies without reducing their DRs.
The present invention relates to gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage with an integrator, a multi-bit quantizer, and a multi-bit DAC, the multi-bit quantizer is companded to cause a feedback signal produced by the multi-bit DAC to have a first gain, with respect to an integrated signal received by the multi-bit quantizer, set greater than one. A second gain, of the integrator, is reduced so that an overall gain of the modulator stage remains equal to one. A third gain, of a stability correction gain element connected to an input of the modulator stage, is increased so that a swing of the integrated signal produced by the integrator remains within a dynamic range of an operational amplifier used to implement the integrator, and the multistage delta sigma modulator can realize the higher SNR. Preferably, but not by way of limitation, the third gain is set equal to a power of two as this enables a noise cancellation logic stage of the delta sigma modulator to have a traditional configuration.
In an embodiment, a multistage delta sigma modulator comprises a first modulator stage having an input capable of receiving an analog signal, a coupling stage connected to the first modulator stage, a second modulator stage connected to the coupling stage, and a noise cancellation logic stage having an output and connected to the first modulator stage and the second modulator stage.
Preferably, the first modulator stage has a single-bit quantizer. Optionally, the first modulator stage has more than one integrator. Alternatively, more than one modulator stage and more than one coupling stage can precede the second modulator stage.
The coupling stage has a stability correction gain element. The second modulator stage has one or more integrators, a companded multi-bit quantizer, and a multi-bit DAC. The companded multi-bit quantizer is capable of causing a feedback analog signal, produced by the multi-bit DAC, to have a first gain, with respect to an integrated signal received by the companded multi-bit quantizer, set greater than one. Each integrator has a second gain set so that an overall gain of the second modulator stage is equal to one. The stability correction gain element has a third gain set to a value capable of ensuring that a swing of the integrated signal remains within a dynamic range of an operational amplifier used to implement the integrator.
By setting the third gain to the highest value within this constraint, the multistage delta sigma modulator can realize its highest SNR. However, the value must also be selected so that a quantized signal produced by the second modulator stage can be processed by the noise cancellation logic stage. Preferably, the third gain is set equal to a power of two.
In another embodiment, a 2-1-1 delta sigma modulator comprises an input capable of receiving an analog signal, a single-bit first modulator stage connected to the input, a first coupling stage connected to the first modulator stage, a single-bit second modulator stage connected to the first coupling stage, a second coupling stage connected to the second modulator stage, a third companded two-bit modulator stage connected to the second coupling stage, and a noise cancellation logic stage having an output and connected to the first modulator stage, the second modulator stage, and the third modulator stage.
The second coupling stage has a stability correction gain element with a first gain set equal to one. The third modulator stage has an integrator, a companded two-bit quantizer, and a two-bit DAC. The integrator has a second gain set equal to xe2x80x9caxe2x80x9d. The companded two-bit quantizer and the two-bit DAC have a combined gain set equal to 1/a.